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Ordering number : EN*5440
MOS LSI
LC89950
1H Delay Line for PAL Systems
Preliminary Overview
The LC89950 is an IC that provides 1H delay processing for color difference signals used in PAL and SECAM format TV. The LC89950 has two CCD systems, one for the R-Y and one for the B-Y signal, and drives these CCDs with a 4-MHz clock generated within the IC. It uses a sandcastle-shaped three-value input clock with a 1 H (64 s) period. * Auto-bias and input clamping circuits * 4-MHz output circuit
Package Dimensions
unit: mm
3003A-DIP14
[LC89950]
Features
* 5-V single-voltage power supply * Two input and output systems, one each for R-Y and BY signals * Takes a sandcastle pulse (SCP) as the input clock, and converts that to a burst gate pulse (BGP) signal internally. * Generates the CCD drive pulses (4 MHz) from the input clock using a PLL circuit. * Uses BGP as clamp pulses and clamps the no signal section (back porch) once every horizontal scan period. * The output signal is in-phase with the input signal
SANYO: DIP14
Functions
* * * * * Two on-chip 254.5-bit CCD shift registers CCD drive circuits Sample-and-hold circuit Burst gate pulse detection circuit 256 x PLL circuit
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD Pd max Topr Tstg Conditions Ratings -0.3 to +6.0 450 -10 to +60 -55 to +125 Unit V mW C C
Allowable Operating Ranges at Ta = 25C
Parameter Supply voltage Input signal amplitude Symbol VDD VINPP(R-Y) VINPP(B-Y) Conditions min 4.75 typ 5.0 500 500 max 5.25 700 700 Unit V mV mV
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D3097HA(OT) No. 5440-1/5
LC89950 Electrical Characteristics at Ta = 25C, VDD = 5.0 V, Fscp = 15.625 kHz
Switch States Parameter Current drain Output pin voltage (pin 1) Output pin voltage (pin 3) Input pin voltage (pin 7) Input pin voltage (pin 5) Voltage gain Differential voltage gain Frequency characteristics Symbol SW1 IDD VOUT (R-Y) VOUT (B-Y) VIN (R-Y) VIN (B-Y) GV (R-Y) GV (B-Y) GV Gf (R-Y) Gf (B-Y) +L6 (R-Y) +L6 (B-Y) -L6 (R-Y) -L6 (B-Y) Lclk (R-Y) Lclk (B-Y) No (R-Y) No (B-Y) ZOUT (R-Y) ZOUT (B-Y) Td (R-Y) Td (B-Y) a/b b a b a a b ab a b a b a b a b a b a b a b SW2 a a a a a a a a a a a a a a a a a a ab ab a a SW3 a/b a/b a/b a/b a/b a a a a a a a b b a a a a a a a a SW4 a/b a/b a/b a/b a/b a a a a a b b b b a a b b a a a a Test conditions 1 2 2 2 2 3 3 3 4 4 5 5 5 5 6 6 7 7 8 8 9 9 200 200 -3 -3 57 57 57 57 min 5 0.7 0.7 1.4 1.4 -2 -2 typ 10 1.7 1.7 2.4 2.4 0 0 0.1 -1 -1 60 60 60 60 7 7 1 1 300 300 63.80 63.80 63 63 63 63 12 12 2 2 400 400 max 15 2.7 2.7 3.4 3.4 +2 +2 0.3 Unit mA V V V V dB dB dB dB dB % % % % mVrms mVrms mVrms mVrms s s
Positive phase input linearity +L6
Inverted input linearity
-L6
Clock leakage (4 MHz)
Noise level
Output impedance
Delay time
Sandcastle Pulse (Input Clock) Conditions
Parameter Input frequency*1 Input pulse width High level*2 Mid level*3 Low level Symbol Fscp TW bgp Vhigh Vmid Vlow Conditions min 14.625 3.0 5.9 2.5 -0.3 typ 15.625 4.0 6.5 3.5 0 max 16.625 5.0 7.5 4.4 2.5 Unit kHz s V V V
Notes: 1. Indicates the synchronization range for the PLL circuit. The delay time changes with the input frequency. 2. Vhigh is the minimum value between c and d. 3. Vmid is the maximum value between a and b and between e and f.
No. 5440-2/5
LC89950 Test Conditions 1. Measure the power-supply current when no input signal is supplied. 2. Measure the pin voltages on each pin when no input signal is supplied. 3. Let VOUT be the OUT pin signal amplitude when a 200-kHz 350-mVp-p sine wave is input. Then, the voltage gain (GV) for each of the R-Y and B-Y I/O systems is given by: VOUT [mVp-p] GV = 20log -------------- [dB] 350 [mVp-p] The R-Y and B-Y voltage gains (GV) are: GV = | GV (R-Y) -GV (B-Y)| 4. Let V1 be the OUT pin output when a 100-kHz 200-mVp-p sine wave is input. Let V2 be the OUT pin output when a 1-MHz 200-mVp-p sine wave is input. V2 [mVp-p] Gf = 20log -------------- [dB] V1 [mVp-p] 5. Input a 5-stage step waveform (350 mVp-p) and measure the levels a and b in the output signals. Perform those measurements for both positive phase and inverted signal inputs.

6. Measure the noise spectrum of the output signal when no input is supplied and read the 4-MHz peak. 7. Pass the output signal through a 2-MHz low-pass filter and a 100-kHz high-pass filter. Then, measure that output with a noise meter, when no input signal is supplied. Use a 2-MHz low-pass filter with an attenuation of -60 dB at 4-MHz. 8. Input a 200-kHz 350-mVp-p sine wave. Let V1 be the OUT pin output when SW2 is set to a. Let V2 be the OUT pin output when SW2 is set to b. V1 [mVp-p] - V2 [mVp-p] ZO = ------------------------ x 500 [] V2 [mVp-p] 9. Measure the delay time of the OUT pin output with respect to the input signal. When taking this measurement, exclude the delay associated with the low-pass filter.
No. 5440-3/5
LC89950 Pin Assignment
Note: Pins 1 and 3 are referred to collectively as the "OUT pin."
Block Diagram
No. 5440-4/5
LC89950 Test Circuit
Notes: 1. Adjust VR (2 k) so that the output amplitudes when SW3 is set to the a and b positions are equal. 2. LPF is a 2-MHz low-pass filter. Use a filter with an attenuation of -60 dB at 4 MHz. 3. The operational amplifier (AD842JN) is a non-inverting amplifier, and the gain from the SW1 output to the operational amplifier output should be 0 dB.
Sample Application Circuit
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5440-5/5

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